SH7751 Datasheet, PDF (80/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figure 14.3 Round Robin Mode ................................................................................................ 524
Figure 14.4 Example of Changes in Priority Order in Round Robin Mode............................... 525
Figure 14.5 Data Flow in Single Address Mode ....................................................................... 527
Figure 14.6 DMA Transfer Timing in Single Address Mode.................................................... 528
Figure 14.7 Operation in Dual Address Mode........................................................................... 529
Figure 14.8 Example of Transfer Timing in Dual Address Mode ............................................. 530
Figure 14.9 Example of DMA Transfer in Cycle Steal Mode ................................................... 531
Figure 14.10 Example of DMA Transfer in Burst Mode............................................................. 531
Figure 14.11 Bus Handling with Two DMAC Channels Operating............................................ 535
Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ
(Level Detection), DACK (Read Cycle) ................................................................ 538
Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ
(Edge Detection), DACK (Read Cycle) ................................................................. 539
Figure 14.14 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ
(Level Detection), DACK (Read Cycle) ................................................................ 540
Figure 14.15 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ
(Edge Detection), DACK (Read Cycle) ................................................................. 541
Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection)
→ External Bus ...................................................................................................... 542
Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus → On-Chip SCI
(Level Detection).................................................................................................... 543
Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ
(Level Detection).................................................................................................... 544
Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ
(Edge Detection) .................................................................................................... 545
Figure 14.20 Single Address Mode/Burst Mode External Bus → External Bus/DREQ
(Level Detection).................................................................................................... 546
Figure 14.21 Single Address Mode/Burst Mode External Bus → External Bus/DREQ
(Edge Detection) .................................................................................................... 547
Figure 14.22 Single Address Mode/Burst Mode External Bus → External Bus/DREQ
(Level Detection)/32-Byte Block Transfer (Bus Width: 32 Bits, SDRAM:
Row Hit Write)....................................................................................................... 548
Figure 14.23 On-Demand Transfer Mode Block Diagram .......................................................... 553
Figure 14.24 System Configuration in On-Demand Data Transfer Mode................................... 555
Figure 14.25 Data Transfer Request Format ............................................................................... 556
Figure 14.26 Single Address Mode/Synchronous DRAM → External Device Longword
Transfer SDRAM Auto-Precharge Read Bus Cycle, Burst
(RCD = 1, CAS latency = 3, TPC = 3)................................................................... 559
Rev.4.00 Oct. 10, 2008 Page lxxx of xcviii
REJ09B0370-0400