SH7751 Datasheet, PDF (329/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Pipelining
Functional
Category No. Instruction
Instruc-
Execu-
Lock
tion Issue
tion
Group Rate Latency Pattern Stage Start Cycles
Fixed-point 63
arithmetic
instructions
64
65
DIV0U
DIV1
Rm,Rn
DMULS.L Rm,Rn
EX
1
1
EX
1
1
CO
2
4/4
#1
— ——
#1
— ——
#34
F1 4
2
66 DMULU.L Rm,Rn
CO
2
4/4
#34
F1 4
2
67 DT
Rn
EX
1
1
#1
— ——
68 MAC.L @Rm+,@Rn+
CO
2
2/2/4/4 #35
F1 4
2
69 MAC.W @Rm+,@Rn+
CO
2
2/2/4/4 #35
F1 4
2
70 MUL.L Rm,Rn
CO
2
4/4
#34
F1 4
2
71 MULS.W Rm,Rn
CO
2
4/4
#34
F1 4
2
72 MULU.W Rm,Rn
CO
2
4/4
#34
F1 4
2
73 NEG
Rm,Rn
EX
1
1
#1
— ——
74 NEGC Rm,Rn
EX
1
1
#1
— ——
75 SUB
Rm,Rn
EX
1
1
#1
— ——
76 SUBC
Rm,Rn
EX
1
1
#1
— ——
77 SUBV
Rm,Rn
EX
1
1
#1
— ——
Logical
78 AND
instructions _{79 AND}
Rm,Rn
#imm,R0
EX
1
1
EX
1
1
#1
— ——
#1
— ——
80 AND.B #imm,@(R0,GBR) CO
4
4
#6
— ——
81 NOT
Rm,Rn
EX
1
1
#1
— ——
82 OR
Rm,Rn
EX
1
1
#1
— ——
83 OR
#imm,R0
EX
1
1
#1
— ——
84 OR.B
#imm,@(R0,GBR) CO
4
4
#6
— ——
85 TAS.B @Rn
CO
5
5
#7
— ——
86 TST
Rm,Rn
MT
1
1
#1
— ——
87 TST
#imm,R0
MT
1
1
#1
— ——
88 TST.B #imm,@(R0,GBR) CO
3
3
#5
— ——
89 XOR
Rm,Rn
EX
1
1
#1
— ——
90 XOR
#imm,R0
EX
1
1
#1
— ——
91 XOR.B #imm,@(R0,GBR) CO
4
4
#6
— ——
Rev.4.00 Oct. 10, 2008 Page 231 of 1122
REJ09B0370-0400