SH7751 Datasheet, PDF (1071/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
• Support for the PCI power management control configuration register;
• Support for the power-down/restore request interrupts from hosts on the PCI bus.
There are three configuration registers for PCI power management control. PCI configuration
register 13 shows the address offset (CAPPTR) of the configuration registers for power
management. In the PCIC, this offset is fixed at CAPPTR = H'40. PCI configuration register 16
and PCI configuration register 17 are power management registers. They support two states:
power state D0 (normal) and power state D3 (power down mode).
The PCIC detects when the power state (PWRST) bit of the PCI configuration register 17 changes
(when it is written to from an external PCI device), and issues a power management interrupt. To
control the power management interrupts, there are a PCI power management interrupt register
(PCIPINT) and PCI power management interrupt mask register (PCIPINTM). Of the power
management interrupts, the power state D3 (PWRST_D3) interrupt detects a transition from the
power state D0 to D3, while power state D0 (PWRST_D0) interrupt detects a transition from the
power state D3 to D0. Interrupt masks can be set for each interrupt.
No power state D0 interrupt is generated at a power-on reset.
The following cautions should be noted when the PCIC is operating in non-host mode and a power
down interrupt is received from the host:
In PCI power management (version 1.0 compatible), the PCI bus clock stops within a minimum of
16 clocks after the host device has instructed a transition to power state D3. After detecting a
power state D3 (power down) interrupt, do not, therefore, attempt to read or write to local registers
that can be accessed from the CPU and PCI bus. Because these registers operate using the PCI bus
clock, the read/write cycle for these registers will not be completed if the clock stops.
22.9.2 Stopping the Clock
Power savings can be achieved by stopping the bus clock used by the PCIC and the PCI bus clock.
The PCI clock control register (PCICLKR) is provided for controlling the PCIC clock. Regarding
the control register for stopping the peripheral module clock (Pck) in the PCIC, refer to section 9,
Power-Down Modes.
The method of stopping the clock differs according to the operating mode of the PCI bus clock.
See table 22.14.
Rev.4.00 Oct. 10, 2008 Page 973 of 1122
REJ09B0370-0400