SH7751 Datasheet, PDF (107/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

1.2 Block Diagram
Figure 1.1 shows an internal block diagram of the SH7751/SH7751R Group.
1. Overview
CPU
UBC
FPU
Lower 32-bit data
SH-4 Core
I cache
ITLB
Cache and
TLB
controller
UTLB
O cache
CPG
INTC
SCI
(SCIF)
RTC
BSC
DMAC
TMU
PCIC
(PCI)DMAC
32-bit
PCI
address/
data
External (SH) bus
interface
26-bit
SH bus
address
32-bit
SH bus
data
Legend:
BSC: Bus state controller
CPG: Clock pulse generator
DMAC: Direct memory access controller
FPU: Floating-point unit
INTC: Interrupt controller
ITLB: Instruction TLB (translation lookaside buffer)
UTLB: Unified TLB (translation lookaside buffer)
RTC: Realtime clock
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO
TMU: Timer unit
UBC: User break controller
PCIC: PCI bus controller
Figure 1.1 Block Diagram of SH7751/SH7751R Group Functions
Rev.4.00 Oct. 10, 2008 Page 9 of 1122
REJ09B0370-0400