SH7751 Datasheet, PDF (425/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. Timer Unit (TMU)
12.3 Operation
Each channel has a 32-bit timer counter (TCNT) that performs count-down operations, and a 32-
bit timer constant register (TCOR). The channels have an auto-reload function that allows cyclic
count operations, and can also perform external event counting. Channel 2 also has an input
capture function.
12.3.1 Counter Operation
When one of bits STR0–STR4 is set to 1 in the timer start register (TSTR, TSTR2), the timer
counter (TCNT) for the corresponding channel starts counting. When TCNT underflows, the UNF
flag is set in the corresponding timer control register (TCR). If the UNIE bit in TCR is set to 1 at
this time, an interrupt request is sent to the CPU. At the same time, the value is copied from
TCOR into TCNT, and the count-down continues (auto-reload function).
Example of Count Operation Setting Procedure: Figure 12.2 shows an example of the count
operation setting procedure.
1. Select the count clock with bits TPSC2–TPSC0 in the timer control register (TCR). When an
external clock in channels 0 to 2 is selected, set the TCLK pin to input mode with the TCOE
bit in TOCR, and select the external clock edge with bits CKEG1 and CKEG0 in TCR.
2. Specify whether an interrupt is to be generated on TCNT underflow with the UNIE bit in TCR.
3. When the input capture function is used, set the ICPE bits in TCR, including specification of
whether the interrupt function is to be used.
4. Set a value in the timer constant register (TCOR).
5. Set the initial value in the timer counter (TCNT).
6. Set the STR bit to 1 in the timer start register (TSTR, TSTR2) to start the count.
Rev.4.00 Oct. 10, 2008 Page 327 of 1122
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