SH7751 Datasheet, PDF (387/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Clock Oscillation Circuits
10.11 Usage Notes
10.11.1 Invalid Manual Reset Triggered by Watchdog Timer (SH7751 Only)
Under certain conditions the on-chip watchdog timer (WDT) may trigger an invalid manual reset.
Conditions Under which Problem Occurs: The on-chip WDT triggers an invalid manual reset
when all of the following four conditions are satisfied.
1. After the WDT overflows, regardless of the values of the WT/IT and RSTS bits in WTCSR.
2. Before the counter (WTCNT) is incremented by the clock specified by the WTCSR.CKS bit.
3. The value of at least one of the TME, WT/IT, and RSTS bits in WTCSR is 0.
4. A value of 1 is written to the TME, WT/IT, and RSTS bits in WTCSR.
Workaround: A workaround for this problem is to use software to increment WTCNT before
writing 1 to the TME, WT/IT, and RSTS bits in WTCSR. Specific lines of code for this purpose
are listed below.
Example: Add the following lines of code before the instructions for writing 1 to the TME,
WT/IT, and RSTS bits in WTCSR.
MOV.L #WTCNT,R7
MOV.W #H'5A00,R8
MOV.W R8,@R7
MOV.L #WTCSR,R9
MOV.W #H'A580,R10
MOV.W R10,@R9
L.OOP_WDT:
MOV.B @R7,R0
CMP/EQ #H'00, R0
BT
L.OOP_WDT
Rev.4.00 Oct. 10, 2008 Page 289 of 1122
REJ09B0370-0400