SH7751 Datasheet, PDF (482/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
Bits 15 and 14—PCMCIA Wait (A5PCW1, A5PCW0): These bits specify the number of waits
to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The
setting of these bits is selected when the PCMCIA interface access TC bit is 0.
Bit 15: A5PCW1
0
1
Bit 14: A5PCW0
0
1
0
1
Waits Inserted
0 (Initial value)
15
30
50
Bits 13 and 12—PCMCIA Wait (A6PCW1, A6PCW0): These bits specify the number of waits
to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The
setting of these bits is selected when the PCMCIA interface access TC bit is 0.
Bit 13: A6PCW1
0
1
Bit 12: A6PCW0
0
1
0
1
Waits Inserted
0 (Initial value)
15
30
50
Bits 11 to 9—Address-OE/WE Assertion Delay (A5TED2–A5TED0): These bits set the delay
time from address output to OE/WE assertion on the connected PCMCIA interface. The setting of
these bits is selected when the PCMCIA interface access TC bit is 0.
Bit 11: A5TED2
0
1
Bit 10: A5TED1
0
1
0
1
Bit 9: A5TED0
0
1
0
1
0
1
0
1
Waits Inserted
0 (Initial value)
1
2
3
6
9
12
15
Rev.4.00 Oct. 10, 2008 Page 384 of 1122
REJ09B0370-0400