SH7751 Datasheet, PDF (441/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
6. A 64-bit access size applies only to transfer by the DMAC (CHCRn.TS = 000).
In the case of access to external memory by means of FMOV (FPSCR.SZ = 1), two
32-bit access size transfers are performed.
Area 0: H'00000000 SRAM/burst ROM/MPX
Area 1: H'04000000 SRAM/MPX/byte control SRAM
Area 2: H'08000000 SRAM/synchronous DRAM/MPX
Area 3: H'0C000000
Area 4: H'10000000
SRAM/synchronous DRAM/DRAM/
MPX
SRAM/MPX/byte control SRAM
Area 5: H'14000000 SRAM/burst ROM/PCMCIA/MPX
Area 6: H'18000000 SRAM/burst ROM/PCMCIA/MPX
The PCMCIA interface is
for memory and I/O card use
Figure 13.3 External Memory Space Allocation
Memory Bus Width: In this LSI, the memory bus width can be set independently for each space.
For area 0, a bus size of 8, 16, or 32 bits can be selected in a power-on reset by means of the
RESET pin, using external pins. The relationship between the external pins (MD4 and MD3) and
the bus width in a power-on reset is shown below.
MD4
0
1
MD3
0
1
0
1
Bus Width
Reserved
8 bits
16 bits
32 bits
When SRAM interface or ROM is used in areas 1 to 6, a bus width of 8, 16, or 32 bits can be
selected with bus control register 2 (BCR2). When burst ROM is used, a bus width of 8, 16, or 32
bits can be selected. When byte control SRAM interface is used, a bus width of 16, or 32 bits can
be selected. When the MPX interface is used, a bus width of 32 bit can be set. When the DRAM
interface is used, a bus width of 16, or 32 bits can be selected with the memory control register
(MCR). For the synchronous DRAM interface, set a bus width of 32 bit in the MCR register.
Rev.4.00 Oct. 10, 2008 Page 343 of 1122
REJ09B0370-0400