SH7751 Datasheet, PDF (654/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
• TDACK: Reply strobe signal for external device from DMAC
The assertion timing is the same as the DACKn assertion timing for each memory interface.
However, note that TDACK is an active-low signal.
• ID1, ID0: Channel number notification signals
⎯ 00: Channel 0
⎯ 01: Channel 1
⎯ 10: Channel 2
⎯ 11: Channel 3
Data Transfer Request Format (DTR)
31 29 28 27 26 25 24 23
0
SZ
ID MD
(Reserved)
(Reserved)
Figure 14.25 Data Transfer Request Format
The data transfer request format (DTR format) consists of 32 bits. In the case of normal data
transfer mode (channel 0, except channel 0) and the handshake protocol using the data bus,
channel number and transfer request mode are specified. Connection is made to D31 through D0.
Bits 31 to 29: Transmit Size (SZ2–SZ0)
• 000: DTR format selected
• 001: Setting prohibited
• 010: Setting prohibited
• 011: Setting prohibited
• 100: Setting prohibited
• 101: Setting prohibited
• 110: Request queue clear specification
• 111: Transfer end specification
Bit 28: Reserved
Bits 27 and 26: Channel Number (ID1, ID0)
• 00: Channel 0
• 01: Channel 1
• 10: Channel 2
Rev.4.00 Oct. 10, 2008 Page 556 of 1122
REJ09B0370-0400