SH7751 Datasheet, PDF (1069/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
22.6.3 INTA
When the PCIC is operating as a non-host device, the INTA output can be used for interrupts to
the host device. INTA can be asserted (Low output)/negated (High output) using the INTA output
soft control bit (INTA) of the PCI control register (PCICR). INTA is open collector output.
22.7 Error Detection
The PCIC can store error information generated on the PCI bus. The address information (ALOG
[31:0]) at the time of the error is stored in the PCI error address data register (PCIALR). The PCI
error command information register (PCICLR) stores the type of transfer (MSTPIO, MSTDMA0,
MSTDMA1, MSTDMA2, MSTDMA3, TGT) at the time of the error, and the PCI command
(CMDLOG [3:0]). When the PCIC is operating as host, the PCI error bus master information
register (PCIBMLR) stores the bus master information (REQ4ID, REQ3ID, REQ2ID, REQ1ID,
REQ0ID) at the time of the error.
The error information storage circuit can only store information for one error. Therefore, when
errors occur consecutively, no information is stored for the second or subsequent errors.
Error information is cleared by resets.
22.8 PCIC Clock
Three clocks are used with the PCIC. The peripheral module clock (Pck) is used for PCIC register
access and PIO transfers. The bus clock (Bck) is used for local bus control. The PCI bus clock is
used for PCI bus operation.
The peripheral module clock and PCI bus clock do not need to be in sync, and there is no
particular limit on the frequency ratio. However, in PIO transfers and when registers are being
accessed, etc., circuits operating with the peripheral module clock and circuits operating with the
PCI bus clock and circuits that synchronize both clocks are used, so the transfer speed depends on
the frequency of the peripheral module clock as well.
The bus clock (Bck) and PCI bus clock do not need to be in sync. However, the PCI bus clock
should be set to the same frequency as the bus clock (Bck) or lower.
The maximum PCI bus clock is 66 MHz.
Either of the following can be selected using MD9 as the PCI bus clock: the CKIO feedback input
clock and the clock input from the external input pin (PCICLK).
Rev.4.00 Oct. 10, 2008 Page 971 of 1122
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