SH7751 Datasheet, PDF (711/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Serial Communication Interface (SCI)
Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI.
Bit 4: RE
Description
0
Reception disabled*¹
(Initial value)
1
Reception enabled*²
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which
retain their states.
2. Serial reception is started in this state when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode.
SCSMR1 setting must be performed to decide the receive format before setting the RE
bit to 1.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE bit setting is only valid in asynchronous mode when the MP bit in SCSMR1 is set to 1.
The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0.
Bit 3: MPIE
0
Description
Multiprocessor interrupts disabled (normal reception performed) (Initial value)
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
1
Multiprocessor interrupts enabled*
Note: * When receive data including MPB = 1 is received, the MPIE bit is cleared to 0
automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in
SCSCR1 are set to 1) and FER and ORER flag setting is enabled.
Bit 2—Transmit-End interrupt Enable (TEIE): Enables or disables transmit-end interrupt
(TEI) request generation when there is no valid transmit data in SCTDR1 at the time for MSB data
transmission.
Bit 2: TEIE
Description
0
Transmit-end interrupt (TEI) request disabled*
(Initial value)
1
Transmit-end interrupt (TEI) request enabled*
Note: * TEI interrupt requests can be cleared by reading 1 from the TDRE flag in SCSSR1,
then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0.
Rev.4.00 Oct. 10, 2008 Page 613 of 1122
REJ09B0370-0400