SH7751 Datasheet, PDF (775/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Serial Communication Interface with FIFO (SCIF)
16.2.5 Serial Mode Register (SCSMR2)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
7
—
Initial value:
0
R/W: R
6
5
4
3
2
1
0
CHR
PE
O/E STOP
—
CKS1 CKS0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
SCSMR2 is a 16-bit register used to set the SCIF's serial transfer format and select the baud rate
generator clock source.
SCSMR2 can be read or written to by the CPU at all times.
SCSMR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Bits 15 to 7—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 6—Character Length (CHR): Selects 7 or 8 bits as the asynchronous mode data length.
Bit 6: CHR
Description
0
8-bit data
(Initial value)
1
7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of SCFTDR2 is not transmitted.
Bit 5—Parity Enable (PE): Selects whether or not parity bit addition is performed in
transmission, and parity bit checking in reception.
Bit 5: PE
Description
0
Parity bit addition and checking disabled
(Initial value)
1
Parity bit addition and checking enabled*
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to
transmit data before transmission. In reception, the parity bit is checked for the parity
(even or odd) specified by the O/E bit.
Rev.4.00 Oct. 10, 2008 Page 677 of 1122
REJ09B0370-0400