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SH7751 Datasheet, PDF (1098/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer
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23. Electrical Characteristics
Table 23.18 Clock and Control Signal Timing (HD6417751BP167 (V), HD6417751F167 (V))
VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to 75°C, CL = 30 pF
Item
Symbol Min
Max Unit Figure
EXTAL
clock input
frequency
PLL1/PLL2
operating
1/2 divider operating
fEX
1/2 divider not operating fEX
PLL1/PLL2 not 1/2 divider operating
fEX
operating
1/2 divider not operating fEX
EXTAL clock input cycle time
tEXcyc
EXTAL clock input low-level pulse width
tEXL
EXTAL clock input high-level pulse width
tEXH
EXTAL clock input rise time
tEXr
EXTAL clock input fall time
tEXf
CKIO clock PLL2 operating
fOP
output
PLL2 not operating
fOP
CKIO clock output cycle time
tcyc
CKIO clock output low-level pulse width
tCKOL1
CKIO clock output high-level pulse width
tCKOH1
CKIO clock output rise time
tCKOr
CKIO clock output fall time
tCKOf
CKIO clock output low-level pulse width
tCKOL2
CKIO clock output high-level pulse width
tCKOH2
Power-on oscillation settling time
tOSC1
Power-on oscillation settling time/mode settling
tOSCMD
MD reset setup time
tMDRS
MD reset hold time
tMDRH
RESET assert time
tRESW
30
15
2
1
17.8
3.5
3.5
—
—
30
1
11.9
1
1
—
—
3
3
10
10
3
20
20
56
28
56
28
1000
—
—
4
4
84
84
1000
—
—
3
3
—
—
—
—
—
—
—
MHz
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ms
ms
tcyc
ns
tcyc
23.1
23.1
23.1
23.1
23.1
23.2 (1)
23.2 (1)
23.2 (1)
23.2 (1)
23.2 (1)
23.2 (2)
23.2 (2)
23.3, 23.5
23.3, 23.5
23.3, 23.5
23.3, 23.4, 23.5,
23.6
PLL synchronization settling time
tPLL
200
—
μs 23.9, 23.10
Standby return oscillation settling time 1
tOSC2
10
—
ms 23.4, 23.6
Standby return oscillation settling time 2
tOSC3
5
—
ms 23.7
Standby return oscillation settling time 3
tOSC4
5
—
ms 23.8
IRL interrupt determination time
(RTC used, standby mode)
tIRLSTB
—
200
μs 23.10
TRST reset hold time
tTRSTRH
0
—
ns 23.3, 23.5
Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 28 MHz. When
a 3rd overtone crystal resonator is used, an external tank circuit is necessary.
As there is feedback from the CKIO pin when PLL2 is operating, the load capacitance connected to the
CKIO pin should be a maximum of 50 pF.
Rev.4.00 Oct. 10, 2008 Page 1000 of 1122
REJ09B0370-0400
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