SH7751 Datasheet, PDF (762/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Serial Communication Interface (SCI)
Start of transmission/reception
Read TDRE flag in SCSSR1
No
TDRE = 1?
Yes
Write transmit data
to SCTDR1 and clear TDRE flag
in SCSSR1 to 0
1. SCI status check and transmit data
write:
Read SCSSR1 and check that the
TDRE flag is set to 1, then write
transmit data to SCTDR1 and clear
the TDRE flag to 0. Transition of the
TDRE flag from 0 to 1 can also be
identified by a TXI interrupt.
2. Receive error handling:
If a receive error occurs, read the
ORER flag in SCSSR1 , and after
performing the appropriate error
handling, clear the ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to 1.
3. SCI status check and receive data
Read ORER flag in SCSSR1
read:
Read SCSSR1 and check that the
RDRF flag is set to 1, then read the
ORER = 1?
Yes
receive data in SCRDR1 and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
No
Error handling identified by an RXI interrupt.
Read RDRF flag in SCSSR1
No
RDRF = 1?
Yes
Read receive data in SCRDR1,
and clear RDRF flag
in SCSSR1 to 0
No
All data transferred?
Yes
Clear TE and RE bits
in SCRSR1 to 0
End of transmission/reception
4. Serial transmission/reception
continuation procedure:
To continue serial transmission/
reception, finish reading the RDRF
flag, reading SCRDR1, and clearing
the RDRF flag to 0, before the MSB
(bit 7) of the current frame is received.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible, then write data to
SCTDR1 and clear the TDRE flag to
0.
(Checking and clearing of the TDRE
flag is automatic when the DMAC is
activated by a transmit-data-empty
interrupt (TXI) request, and data is
written to SCTDR1. Similarly, the
RDRF flag is cleared automatically
when the DMAC is activated by a
receive-data-full interrupt (RXI)
request and the SCRDR1 value is
read.)
Note: When switching from transmit or receive operation to simultaneous transmit and receive
operations, first clear the TE bit and RE bit to 0, then set both these bits to 1.
Figure 15.24 Sample Flowchart for Serial Data Transmission and Reception
Rev.4.00 Oct. 10, 2008 Page 664 of 1122
REJ09B0370-0400