SH7751 Datasheet, PDF (14/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
5.3.2 Exception
Handling Vector
Addresses
Page
139
5.4 Exception Types 142
and Priorities
Table 5.2 Exceptions
5.5.3 Exception
146
Requests and BL Bit
5.6.1 Resets
147
(1) Power-On Reset
(2) Manual Reset
148
Revision (See Manual for Details)
Description amended
The reset vector address is fixed at H'A000 0000. General
exception and interrupt vector addresses are determined by
adding the offset for the specific event to the vector base
address, which is set by software in the vector base register
(VBR). …
Table amended
Exception Execution
Category Mode
Exception
Interrupt
Completion Peripheral PCIC
type
module
interrupt
(module/
source)
PCISERR
PCIERR
Priority Priority Vector
Level Order Address
4
*2
(V BR)
Exception
Offset Code
H'600 H'A00
H'AE0
Description amended
When the BL bit in SR is 0, general exceptions and interrupts
are accepted.
When the BL bit in SR is 1 and a general exception other than a
user break is generated, the CPU's internal registers and the
registers of the other modules are set to their post-reset state,
and the CPU branches to the same address as in a reset
(H'A000 0000). For the operation in the event of a user break,
see section 20, User Break Controller (UBC).
Description amended
In the initialization processing, the VBR register is set to H'0000
0000, and in SR, the MD, RB, and BL bits are set to 1, the FD
bit is cleared to 0, and the interrupt mask bits (IMASK) are set
to B'1111.
…
SR.IMASK = B'1111;
Description amended
In the initialization processing, the VBR register is set to H'0000
0000, and in SR, the MD, RB, and BL bits are set to 1, the FD
bit is cleared to 0, and the interrupt mask bits (IMASK) are set
to B'1111.
…
SR.IMASK = B'1111;
Rev.4.00 Oct. 10, 2008 Page xiv of xcviii
REJ09B0370-0400