SH7751 Datasheet, PDF (550/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
command is issued in the TMw1 cycle by setting MCR.MRSET to 1 and performing a write to
address H'FF900000 + X or H'FF940000 + X.
Synchronous DRAM mode register setting should be executed once only after power-on reset and
before synchronous DRAM access, and no subsequent changes should be made.
CKIO
TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
D31–D0
CKE
(High)
Figure 13.38 (1) Synchronous DRAM Mode Write Timing (PALL)
Rev.4.00 Oct. 10, 2008 Page 452 of 1122
REJ09B0370-0400