SH7751 Datasheet, PDF (670/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
CKIO
DBREQ
BAVL
TR
Wait for next DMA request
A25–A0
CA
CA
D31–D0
DTR
D0 D1 D2 D3
D0 D1 D2 D3
CMD
TDACK
RD
RD
ID1, ID0
Start of data transfer
Figure 14.44 Single Address Mode/Burst Mode/Level Detection/
External Bus → External Device Data Transfer
CKIO
DBREQ
BAVL
TR
A25–A0
CA
CA
CA
D31–D0
CMD
DQMn
TDACK
DTR
RD
D0
Idle cycle
RD
D2
D3
Idle cycle
RD
Idle cycle
ID1, ID0
Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Quadword/External Bus → External Device Data Transfer
Rev.4.00 Oct. 10, 2008 Page 572 of 1122
REJ09B0370-0400