SH7751 Datasheet, PDF(55/1224 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer

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SH7751 Datasheet, PDF (55/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

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Item

Page Revision (See Manual for Details)

D.1 Pin States

1093,

Table D.1 Pin States in 1094

Reset, Power-Down

State, and Bus-

Released State (PCI

Enable, Disable

Common)

Table D.2 Pin States in 1095

Reset, Power-Down

State, and Bus-

Released State (PCI

Enable)

Table amended

Reset

(Power-On)

Pin Name

WE3/IOICWR

WE2/IOICRD

DRAK1âDRAK0

MD0/SCK2

TxD

I/O Master Slave

OH

PZ

OH

PZ

OL

L

I/O I*17

I*17

I/O PI

PI

Reset

(Manual)

Master Slave

O*4

Z*13

O*4

Z*13

L

I*11

Z*11O

L

I*11

Z*11O

Standby

Z*13O*3

Bus

Released

Z*13O*3

Hard-

ware

Standby Notes

Z

Z*13O*3

Z*13O*3

Z

Z*11O*6 O

Z

DMAC

I*11Z*11O*6 I*11O

I

SCIF

Z*11O*6 O

Z

SCI

Table amended

Pin Name

PCIREQ4

PCIREQ2/

MD9

PCIREQ3/

MD10

Reset

(Power On)

Reset

(Manual)

Non-

I/O Host Host

Non-

Host Host

Standby

Non-

Host Host

Reset

(Software)

Non-

Host Host

Hard-

ware

Standby Notes

I/O PI PZ

Z*10

Z*10

I*10

(IO*11,*16)

Z*10

PI

(IO*10,*16)

PZ

Z

(IO*10,*16)

Values in

paren-

thesis

are when

using

PORT

I/O I*17 I*17

Z*10

Z*10

I*10

(IO*11,*16)

Z*10

PI

(IO*10,*16)

PZ

Z

(IO*10,*16)

Values in

paren-

thesis

are when

using

PORT

I/O I*17 I*17

Z*10

Z*10

I*10

(IO*11,*16)

Z*10

PI

(IO*10,*16)

PZ

Z

(IO*10,*16)

Values in

paren-

thesis

are when

using

PORT

Table D.3 Pin States in 1097

Reset, Power-Down

State, and Bus-

Released State (PCI

Disable)

Table amended

Pin Name

I/O

PCIREQ4

â

PCIREQ2/MD9

I/O

PCIREQ3/MD10

I/O

Reset

(Power-On)

Master Slave

Reset

(Manual)

Master Slave

Hard-

Bus

ware

Standby Released Standby Notes

Z

Z

Z

Z

Z

Z

Z

I*17

I*17

Z

Z

Z

Z

Z

I*17

I*17

Z

Z

Z

Z

Z

Table D.4 Handling of 1099

Pins When PCI Is Not

Used

Table amended

Pin Name

I/O

IDSEL

I

Handling

Pull down to low level when IDSEL is not in use

D.3 Note on Pin

Processing

Newly added

Appendix E

Synchronous DRAM

Address Multiplexing

Tables

1109

Description amended

(9) BUS 32 (64M: 4M Ã 4b Ã 4) Ã 8 *

(128M: 4M Ã 8b Ã 4) Ã 4

Appendix G Power-On 1115 to Replaced

and Power-Off

1118

Procedures

Rev.4.00 Oct. 10, 2008 Page lv of xcviii

REJ09B0370-0400

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