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SH7751 Datasheet, PDF (301/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
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7. Instruction Set
Table 7.8 System Control Instructions
Instruction
CLRMAC
CLRS
CLRT
LDC
Rm,SR
LDC
Rm,GBR
LDC
Rm,VBR
LDC
Rm,SSR
LDC
Rm,SPC
LDC
Rm,DBR
LDC
Rm,Rn_BANK
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDC.L @Rm+,SSR
LDC.L @Rm+,SPC
LDC.L @Rm+,DBR
LDC.L @Rm+,Rn_BANK
LDS
Rm,MACH
LDS
Rm,MACL
LDS
Rm,PR
LDS.L @Rm+,MACH
LDS.L @Rm+,MACL
LDS.L @Rm+,PR
LDTLB
MOVCA.L R0,@Rn
NOP
OCBI
OCBP
@Rn
@Rn
OCBWB @Rn
PREF @Rn
RTE
Operation
Instruction Code
Privileged
0 â MACH, MACL
0000000000101000 â
0âS
0000000001001000 â
0âT
0000000000001000 â
Rm â SR
0100mmmm00001110 Privileged
Rm â GBR
0100mmmm00011110 â
Rm â VBR
0100mmmm00101110 Privileged
Rm â SSR
0100mmmm00111110 Privileged
Rm â SPC
0100mmmm01001110 Privileged
Rm â DBR
0100mmmm11111010 Privileged
Rm â Rn_BANK (n = 0 to 7) 0100mmmm1nnn1110 Privileged
(Rm) â SR, Rm + 4 â Rm
0100mmmm00000111 Privileged
(Rm) â GBR, Rm + 4 â Rm 0100mmmm00010111 â
(Rm) â VBR, Rm + 4 â Rm 0100mmmm00100111 Privileged
(Rm) â SSR, Rm + 4 â Rm 0100mmmm00110111 Privileged
(Rm) â SPC, Rm + 4 â Rm 0100mmmm01000111 Privileged
(Rm) â DBR, Rm + 4 â Rm 0100mmmm11110110 Privileged
(Rm) â Rn_BANK,
Rm + 4 â Rm
0100mmmm1nnn0111 Privileged
Rm â MACH
0100mmmm00001010 â
Rm â MACL
0100mmmm00011010 â
Rm â PR
0100mmmm00101010 â
(Rm) â MACH, Rm + 4 â Rm 0100mmmm00000110 â
(Rm) â MACL, Rm + 4 â Rm 0100mmmm00010110 â
(Rm) â PR, Rm + 4 â Rm
0100mmmm00100110 â
PTEH/PTEL â TLB
0000000000111000 Privileged
R0 â (Rn) (without fetching
cache block)
0000nnnn11000011 â
No operation
0000000000001001 â
Invalidates operand cache block 0000nnnn10010011 â
Writes back and invalidates
operand cache block
0000nnnn10100011 â
Writes back operand cache block0000nnnn10110011 â
(Rn) â operand cache
0000nnnn10000011 â
Delayed branch, SSR/SPC â 0000000000101011 Privileged
SR/PC
T Bit
â
â
0
LSB
â
â
â
â
â
â
LSB
â
â
â
â
â
â
â
â
â
â
â
â
â
â
â
â
â
â
â
â
Rev.4.00 Oct. 10, 2008 Page 203 of 1122
REJ09B0370-0400
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