SH7751 Datasheet, PDF (1002/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
The bus master data holding circuit can only store data for one master. For this reason, no bus
master data is stored for any second or subsequent errors if errors occur consecutively.
Bits 31 to 5—Reserved: These bits always return 0 when read. Always write 0 to these bits when
writing.
Bit 4—REQ4 Error (REQ4ID): Error occurred when device 4 (REQ4) was bus master.
Bit 3—REQ3 Error (REQ3ID): Error occurred when device 3 (REQ3) was bus master.
Bit 2—REQ2 Error (REQ2ID): Error occurred when device 2 (REQ2) was bus master.
Bit 1—REQ1 Error (REQ1ID): Error occurred when device 1 (REQ1) was bus master.
Bit 0—REQ0 Error (REQ0ID): Error occurred when device 0 (REQ0) was bus master.
22.2.27 PCI DMA Transfer Arbitration Register (PCIDMABT)
Bit: 31
30
29
...
11
10
9
8
—
—
—
...
—
—
—
—
Initial value:
0
0
0
...
0
0
0
0
PCI-R/W: R
R
R
...
R
R
R
R
PP Bus-R/W: R
R
R
...
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
— DMABT
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R/W
PP Bus-R/W: R
R
R
R
R
R
R
R/W
The PCI DMA transfer arbitration register (PCIDMABT) is a register that controls the arbitration
mode in the case of DMA transfers. Two types of DMA arbitration mode can be selected: priority-
fixed and pseudo round-robin. This 32-bit read/write register can be accessed from both the PP bus
and PCI bus.
The PCIDMABT register is initialized to H'00000000 at a power-on reset or software reset.
Always write to this register to specify the DMA transfer arbitration mode prior to starting DMA
transfers.
Rev.4.00 Oct. 10, 2008 Page 904 of 1122
REJ09B0370-0400