SH7751 Datasheet, PDF (884/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Interrupt Controller (INTC)
Bits 31 to 0—Interrupt Mask Clear: These bits indicate the existence of an interrupt request
corresponding to each bit. For the correspondence between bits and interrupt sources, see section
19.3.7, INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation.
Bits 31 to 0
0
1
Description
Do not change corresponding interrupt mask
Clear corresponding interrupt mask
19.3.7 INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation
The following shows the relationship between individual bits in the register and interrupt factors.
Table 19.7 Bit Allocation
Bit No.
31 to 10
9
8
7
6
5
4
3
2
1
0
Module
Reserved
TMU
TMU
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
Interrupt
Reserved
TUNI4
TUNI3
PCIERR
PCIPWDWN
PCIPWON
PCIDMA0
PCIDMA1
PCIDMA2
PCIDMA3
PCISERR
Rev.4.00 Oct. 10, 2008 Page 786 of 1122
REJ09B0370-0400