SH7751 Datasheet, PDF (194/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

3. Memory Management Unit (MMU)
31
24 23
Address field _{1 1 1 1 0 0 1 1 0}
31 30 29 28
Data field
PPN
10 9 8 7
0
E
10 9 8 7 6 5 4 3 2 1 0
V
C
Legend:
PPN: Physical page number
V: Validity bit
E: Entry
SZ: Page size bits
PR SZ
SH
PR: Protection key data
C: Cacheability bit
SH: Share status bit
: Reserved bits (0 write value, undefined read value)
Figure 3.14 Memory-Mapped ITLB Data Array 1
3.7.3 ITLB Data Array 2
ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and SA and TC to be written to data array 2 are specified in the data
field.
In the address field, bits [31:23] have the value H'F38 indicating ITLB data array 2, and the entry
is selected by bits [9:8].
In the data field, SA is indicated by bits [2:0], and TC by bit [3].
The following two kinds of operation can be used on ITLB data array 2:
1. ITLB data array 2 read
SA and TC are read into the data field from the ITLB entry corresponding to the entry set in
the address field.
2. ITLB data array 2 write
SA and TC specified in the data field are written to the ITLB entry corresponding to the entry
set in the address field.
Rev.4.00 Oct. 10, 2008 Page 96 of 1122
REJ09B0370-0400