SH7751 Datasheet, PDF (176/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

3. Memory Management Unit (MMU)
with a different ASID and unshared state (SH bit is 0). To avoid this, use workaround
(1) or (2) below.
(1) Purge the UTLB when switching the ASID values (PTEH and ASID) of the current
processing.
(2) Manage the behavior of program instruction addresses in user mode so that no
instruction is executed in an address area (including overrun prefetch of an
instruction) that is registered in the UTLB with a different ASID and unshared
address translation information. Note that accessing a different ASID in single
virtual memory mode can only be used to trigger an exception during data access.
3.4 TLB Functions
3.4.1 Unified TLB (UTLB) Configuration
The unified TLB (UTLB) is so called because of its use for the following two purposes:
1. To translate a virtual address to a physical address in a data access
2. As a table of address translation information to be recorded in the instruction TLB in the event
of an ITLB miss
Information in the address translation table located in external memory is cached into the UTLB.
The address translation table contains virtual page numbers and address space identifiers, and
corresponding physical page numbers and page management information. Figure 3.7 shows the
overall configuration of the UTLB. The UTLB consists of 64 fully-associative type entries. Figure
3.8 shows the relationship between the address format and page size.
Entry 0
Entry 1
Entry 2
ASID [7:0] VPN [31:10] V
ASID [7:0] VPN [31:10] V
ASID [7:0] VPN [31:10] V
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC
Entry 63 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC
Figure 3.7 UTLB Configuration
Rev.4.00 Oct. 10, 2008 Page 78 of 1122
REJ09B0370-0400