SH7751 Datasheet, PDF (28/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
13.3.8 MPX Interface ⎯
Figure 13.64 MPX
Interface Timing 5 (Burst
Read Cycle, AnW = 0,
No External Wait, Bus
Width: 32 Bits, Transfer
Data Size: 32 Bytes)
Figure 13.65 MPX
Interface Timing 6(Burst
Read Cycle, AnW = 0,
External Wait Control,
Bus Width: 32
Bits,Transfer Data Size:
32 Bytes)
Figure 13.66 MPX
Interface Timing 7(Burst
Write Cycle, AnW = 0,
No External Wait, Bus
Width: 32 Bits,Transfer
Data Size: 32 Bytes)
Figure 13.67 MPX
Interface Timing 8(Burst
Write Cycle, AnW = 1,
External Wait Control,
Bus Width: 32
Bits,Transfer Data Size:
32 Bytes)
13.3.9 Byte Control 485
SRAM Interface
Figure 13.64 Example
of 32-Bit Data Width
Byte Control SRAM
Revision (See Manual for Details)
Figures deleted
Figure amended, Note deleted
SH7751/SH7751R
A17–A2
CSn
RD
RD/WR
D31–D16
WE3
WE2
D15–D0
WE1
WE0
Rev.4.00 Oct. 10, 2008 Page xxviii of xcviii
REJ09B0370-0400