SH7751 Datasheet, PDF (342/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Power-Down Modes
Bit 0—Module Stop 0 (MSTP0): Specifies stopping of the clock supply to serial communication
interface channel 1 (SCI) among the on-chip peripheral modules. The clock supply to the SCI is
stopped when the MSTP0 bit is set to 1.
Bit 0: MSTP0
0
1
Description
SCI operates
SCI clock supply is stopped
(Initial value)
9.2.2 Peripheral Module Pin High Impedance Control
When bit 6 in the standby control register (STBCR) is set to 1, peripheral module related pins go
to the high-impedance state in standby mode.
• Relevant Pins
SCI related pins
DMA related pins
SCK
TXD
MD7/CTS2
DACK0
DACK1
MD0/SCK2
MD1/TXD2
MD8/RTS2
DRAK0
DRAK1
• Other Information
The setting in this register is invalid when the above pins are used as port output pins.
For details of pin states, see Appendix D, Pin Functions.
9.2.3 Peripheral Module Pin Pull-Up Control
When bit 5 in the standby control register (STBCR) is cleared to 0, peripheral module related pins
are pulled up when in the input or high-impedance state.
• Relevant Pins
SCI related pins
DMA related pins
TMU related pin
MD0/SCK2
MD7/CTS2
RXD
DREQ0
DREQ1
TCLK
MD1/TXD2
MD8/RTS2
TXD
DACK0
DACK1
MD2/RXD2
SCK
DRAK0
DRAK1
Rev.4.00 Oct. 10, 2008 Page 244 of 1122
REJ09B0370-0400