SH7751 Datasheet, PDF (1075/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
22.11 Version Management
The PCIC version management is written in the revision ID (8 bits) of the PCI configuration
register 2 (PCICONF2).
22.12 Usage Notes
22.12.1 Notes on Arbiter Interrupt Usage (SH7751 Only)
When the PCIC function of the SH7751 is employed as a host with an arbitration function, care
must be exercised as follows with regard to the target bus timeout interrupt and master bus timeout
interrupt in the PCI arbiter interrupt register (PCIAINT).
Description: On the SH7751, notification of violations of the 16-clock rule or 8-clock rule for
external PCI devices (target latency and master data latency clock cycle limitations under the PCI
2.1 specification) are provided by setting bit 12 (target bus timeout interrupt) or bit 11 (master bus
timeout interrupt) in the PCI arbiter interrupt register (PCIAINT) of the PCIC. However, on the
SH7751 these clock cycle limitations are set to one clock cycle fewer than the values defined in
the PCI 2.1 specification.
In other words, in the timings described in 1. and 2. below, even though the target latency or
master data latency of the external PCI device does not violate the 16-clock rule or 8-clock rule
according to the PCI 2.1 specification, the SH7751 judges that a 16-clock rule or 8-clock rule
violation has occurred and sets to 1 bit 12 (target bus timeout interrupt) or bit 11 (master bus
timeout interrupt) in the PCI arbiter interrupt register (PCIAINT).
1. Target latency: A target bus timeout interrupt occurs (see figures 22.24 and 22.25).
During the first data transfer, the external PCI device functioning as the target asserts TRDY or
STOP at the sixteenth clock cycle after the data transfer request from the master device
(FRAME asserted). Alternately, during the second or a subsequent data transfer, it asserts
TRDY or STOP at the eighth clock cycle after the immediately preceding data phase.
2. Master data latency: A master bus timeout interrupt occurs (see figures 22.26 and 22.27).
The external PCI device functioning as the master acquires the bus and asserts FRAME, then
asserts IRDY at the eighth clock cycle during the first data transfer. Alternately, during the
second or a subsequent data transfer, it asserts IRDY at the eighth clock cycle after the
immediately preceding data phase.
Workarounds: When the PCIC function of the SH7751 is employed as a host with an arbitration
function, and an external device is connected that employs the full number of clock cycles
permitted under the 16-clock rule or 8-clock rule, use the PCI arbiter interrupt mask register
(PCIAINTM) to mask the bus timeout interrupts in the PCI arbiter interrupt register (PCIAINT).
Rev.4.00 Oct. 10, 2008 Page 977 of 1122
REJ09B0370-0400