SH7751 Datasheet, PDF (415/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. Timer Unit (TMU)
12.1.4 Register Configuration
Table 12.2 summarizes the TMU registers.
Table 12.2 TMU Registers
Initialization
Chan-
nel Name
Power-
Stand-
Abbre-
On
Manual by
Area 7
viation R/W Reset Reset Mode Initial Value P4 Address Address
Access
Size
Com- Timer
mon output
control
register
TOCR R/W Ini-
Ini-
Held
tialized tialized
H'00
H'FFD80000 H'1FD80000 8
Timer
start
register
TSTR R/W Ini-
Ini-
Ini-
H'00
tialized tialized tialized*¹
H'FFD80004 H'1FD80004 8
Timer TSTR2 R/W Ini-
Held
start
tialized
register 2
Held
H'00
H'FE100004 H'1E100004 8
0
Timer TCOR0 R/W Ini-
Ini-
Held H'FFFFFFFF H'FFD80008 H'1FD80008 32
constant
tialized tialized
register 0
Timer TCNT0 R/W Ini-
Ini-
Held*² H'FFFFFFFF H'FFD8000C H'1FD8000C 32
counter 0
tialized tialized
Timer TCR0
control
register 0
R/W Ini-
Ini-
Held
tialized tialized
H'0000
H'FFD80010 H'1FD80010 16
1
Timer TCOR1 R/W Ini-
Ini-
Held H'FFFFFFFF H'FFD80014 H'1FD80014 32
constant
tialized tialized
register 1
Timer TCNT1 R/W Ini-
Ini-
Held*² H'FFFFFFFF H'FFD80018 H'1FD80018 32
counter 1
tialized tialized
Timer TCR1
control
register 1
R/W Ini-
Ini-
Held
tialized tialized
H'0000
H'FFD8001C H'1FD8001C 16
2
Timer TCOR2 R/W Ini-
Ini-
Held H'FFFFFFFF H'FFD80020 H'1FD80020 32
constant
tialized tialized
register 2
Timer TCNT2 R/W Ini-
Ini-
Held*² H'FFFFFFFF H'FFD80024 H'1FD80024 32
counter 2
tialized tialized
Timer TCR2
control
register 2
R/W Ini-
Ini-
Held
tialized tialized
H'0000
H'FFD80028 H'1FD80028 16
Input
capture
register
TCPR2 R
Held
Held
Held
Undefined H'FFD8002C H'1FD8002C 32
Rev.4.00 Oct. 10, 2008 Page 317 of 1122
REJ09B0370-0400