SH7751 Datasheet, PDF (19/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
10.2.1 Block Diagram 271
of CPG
PLL Circuit 1:
10.3 Clock Operating 273
Modes
Table 10.3 (1) Clock
Operating Modes
(SH7751)
10.3 Clock Operating 274
Modes
Table 10.4 FRQCR
Settings and Internal
Clock Frequencies
Revision (See Manual for Details)
Description added
PLL Circuit 1: PLL circuit 1 has a function for multiplying the
clock frequency from the EXTAL pin or crystal oscillation circuit
by 6 (SH7751 and SH7751R) or 12 (SH7751R). Starting and
stopping is controlled by a frequency control register setting.
Control is performed so that the internal clock rising edge
phase matches the input clock rising edge phase.
Table amended
External
Pin Combination
Clock
Operating
Mode
MD2
MD1 MD0
0
0
0
0
1
1
2
1
0
3
1
4
1
0
0
5
1
6
1
0
1/2
Frequency
Divider
Off
Off
On
Off
On
Off
Off
PLL1
On
On
On
On
On
On
Off
Frequency
(vs. Input Clock)
Peripheral
CPU Bus Module
PLL2 Clock Clock Clock
On 6
3/2 3/2
On 6
1
1
On 3
1
1/2
On 6
2
1
On 3
3/2 3/4
On 6
3
3/2
Off 1
1/2 1/2
FRQCR
Initial Value
H'0E1A
H'0E23
H'0E13
H'0E13
H'0E0A
H'0E0A
H'0808
Table amended
FRQCR
(Lower 9 Bits)
CPU Clock
Frequency Division Ratio of Frequency Divider 2
Bus Clock
Peripheral Module Clock
H'000
1
1
1/2
H'002
1/4
H'004
1/8
H'008
1/2
1/2
H'00A
1/4
H'00C
1/8
H'011
1/3
1/3
H'013
1/6
H'01A
1/4
1/4
H'01C
1/8
H'023
1/6
1/6
H'02C
1/8
1/8
H'048
1/2
1/2
1/2
H'04A
1/4
H'04C
1/8
H'05A
1/4
1/4
H'05C
1/8
H'063
1/6
1/6
H'06C
1/8
1/8
H'091
1/3
1/3
1/3
H'093
1/6
H'0A3
1/6
1/6
H'0DA
1/4
1/4
1/4
H'0DC
1/8
H'0EC
1/8
H'123
1/6
1/6
1/6
H'16C
1/8
1/8
1/8
Note: Do not set values other than those shown in the table for the lower 9 bits of FRQCR.
Rev.4.00 Oct. 10, 2008 Page xix of xcviii
REJ09B0370-0400