SH7751 Datasheet, PDF (923/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

21. High-performance User Debug Interface (H-UDI)
21.1.3 Pin Configuration
Table 21.1 shows the H-UDI pin configuration.
Table 21.1 H-UDI Pins
Pin Name Abbreviation I/O
Function
When Not Used
Clock pin TCK
Mode pin TMS
Reset pin TRST
Data input TDI
pin
Input
Input
Input
Input
Same as the JTAG serial clock input Open*¹
pin. Data is transferred from data input
pin TDI to the H-UDI circuit, and data is
read from data output pin TDO, in
synchronization with this signal.
The mode select input pin. Changing
this signal in synchronization with TCK
determines the meaning of the data
input from TDI. The protocol conforms
to the JTAG (IEEE Std 1149.1)
specification.
Open*¹
The input pin that resets the H-UDI. *^2, *³
This signal is received asynchronously
with respect to TCK, and effects a reset
of the JTAG interface circuit when low.
TRST must be driven low for a certain
period when powering on, regardless of
whether or not JTAG is used. This
differs from the IEEE specification.
The data input pin. Data is sent to
the H-UDI circuit by changing this
signal in synchronization with TCK.
Open*¹
Data output TDO
pin
Emulator pin ASEBRK/
BRKACK
Output
Input/
output
The data output pin. Data is sent to the
H-UDI circuit by reading this signal in
synchronization with TCK.
Dedicated emulator pin
Open
Open*¹
AUDSYNC
AUDCK
AUDATA3–
AUDATA0
Output Dedicated emulator pin
Open
Notes: 1. Pulled up inside the chip. When designing a board that allows use of an emulator, or
when using interrupts and resets via the H-UDI, there is no problem in connecting a
pullup resistance externally.
2. When designing a board that enables the use of an emulator, or when using interrupts
and resets via the H-UDI, drive TRST low for a period overlapping RESET at power-on,
and also provide for control by TRST alone.
Rev.4.00 Oct. 10, 2008 Page 825 of 1122
REJ09B0370-0400