SH7751 Datasheet, PDF (430/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. Timer Unit (TMU)
12.4 Interrupts
There are six TMU interrupt sources, comprising underflow interrupts and the input capture
interrupt (when the input capture function is used). Underflow interrupts are generated on channels
0 to 4, and input capture interrupts on channel 2 only.
An underflow interrupt request is generated (on an individual channel basis) when TCR.UNF = 1
and the channel's interrupt enable bit is 1.
When the input capture function is used and an input capture request is generated, an interrupt is
requested if the input capture input flag (ICPF) in TCR2 is 1 and the input capture control bits
(ICPE1, ICPE0) in TCR2 are 11.
The TMU interrupt sources are summarized in table 12.3.
Table 12.3 TMU Interrupt Sources
Channel
0
1
2
3
4
Interrupt Source
TUNI0
TUNI1
TUNI2
TICPI2
TUNI3
TUNI4
Description
Underflow interrupt 0
Underflow interrupt 1
Underflow interrupt 2
Input capture interrupt 2
Underflow interrupt 3
Underflow interrupt 4
12.5 Usage Notes
12.5.1 Register Writes
When performing a TMU register write, timer count operation must be stopped by clearing the
start bit (STR0–STR4) for the relevant channel in the timer start register (TSTR, TSTR2).
Note that the timer start register (TSTR, TSTR2) can be written to, and the underflow flag (UNF)
and input capture flag (ICPF) of the timer control registers (TRCR0 to TCR4) can be cleared while
the count is in progress. When the flags (UNF and ICPF) are cleared while the count is in
progress, make sure not to change the values of bits other than those being cleared.
Rev.4.00 Oct. 10, 2008 Page 332 of 1122
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