SH7751 Datasheet, PDF (31/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page Revision (See Manual for Details)
14.1.1 Features
14.2.4 DMA Channel
Control Registers 0-3
(CHCR0-CHCR3)
498, 499 Description amended
⎯ On-chip peripheral modules request
…
Note: * DTR.COUNT [7:4] (DTR [23:20]): Sets the port as
not used. In DDT mode on the SH7751, an external
device and the DMAC perform handshaking using
the DBREQ, BAVL, TR, TDACK, ID[1:0], and
D[31:0] signals during data transfer. On the
SH7751R, the DBREQ, BAVL, TR, TDACK, ID[2:0],
and D[31:0] signals are used for handshaking
during data transfer between an external device and
the DMAC.
508
Description added
Bit 28—Source Address Wait Control Select (STC): Specifies
CS5 or CS6 space wait control for PCMCIA interface area
access. This bit selects the wait control register in the BSC that
performs area 5 and 6 wait cycle control.
14.3.4 Types of DMA 533
Transfer
(a) Normal DMA Mode
Table 14.8 External
Request Transfer
Sources and
Destinations in Normal
DMA Mode
Table title amended
(b) DDT Mode
534
Table 14.9 External
Request Transfer
Sources and
Destinations in DDT
Mode
Table amended
Transfer Direction (Settable Memory Interface)
Transfer Source
Transfer Destination
Usable
Address DMAC
Mode Channels
1 Synchronous DRAM
External device with DACK
Single 0, 1, 2, 3
2 External device with DACK
Synchronous DRAM
Single 0, 1, 2, 3
3 Synchronous DRAM
SRAM-type, MPX, PCMCIA * Dual
1, 2, 3
4 SRAM-type, MPX, PCMCIA * Synchronous DRAM
Dual
1, 2, 3
5 SRAM-type, DRAM, PCMCIA,
MPX
SRAM-type, MPX, PCMCIA * Dual
1, 2, 3
6 SRAM-type, MPX, PCMCIA
* SRAM-type, DRAM, PCMCIA,
MPX
Dual
1, 2, 3
Rev.4.00 Oct. 10, 2008 Page xxxi of xcviii
REJ09B0370-0400