SH7751 Datasheet, PDF (484/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
Bits 2 to 0—OE/WE Negation-Address Delay (A6TEH2–A6TEH0): These bits set the address
hold delay time from OE/WE negation in a write on the connected PCMCIA interface or in an I/O
card read. In the case of a memory card read, the address hold delay time from the data sampling
timing is set. The setting of these bits is selected when the PCMCIA interface access TC bit is 0.
Bit 2: A6TEH2
0
1
Bit 1: A6TEH1
0
1
0
1
Bit 0: A6TEH0
0
1
0
1
0
1
0
1
Waits Inserted
0 (Initial value)
1
2
3
6
9
12
15
13.2.10 Synchronous DRAM Mode Register (SDMR)
The synchronous DRAM mode register (SDMR) is a write-only virtual 16-bit register that is
written to via the synchronous DRAM address bus, and sets the mode of the area 2 and area 3
synchronous DRAM.
Settings for the SDMR register must be made before accessing synchronous DRAM.
Bit: 15
14
13
12
11
10
9
8
Initial value: —
—
—
—
—
—
—
—
R/W: W
W
W
W
W
W
W
W
Bit:
7
6
5
4
3
2
1
0
Initial value: —
—
—
—
—
—
—
—
R/W: W
W
W
W
W
W
W
W
Since the address bus, not the data bus, is used to write to the synchronous DRAM mode register,
if the value to be set is “X” and the SDMR register address is “Y”, value “X” is written to the
synchronous DRAM mode register by performing a write to address X + Y. When the
synchronous DRAM bus width is set to 32 bits, as A0 of the synchronous DRAM is connected to
Rev.4.00 Oct. 10, 2008 Page 386 of 1122
REJ09B0370-0400