SH7751 Datasheet, PDF (195/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

3. Memory Management Unit (MMU)
31
24 23
Address field _{1 1 1 1 0 0 1 1 1}
10 9 8 7
0
E
31
Data field
Legend:
TC: Timing control bit
E: Entry
4320
SA
TC
SA: Space attribute bits
: Reserved bits (0 write value, undefined read value)
Figure 3.15 Memory-Mapped ITLB Data Array 2
3.7.4 UTLB Address Array
The UTLB address array is allocated to addresses H'F600 0000 to H'F6FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and VPN, D, V, and ASID to be written to the address array are
specified in the data field.
In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array, and the
entry is selected by bits [13:8]. The address array bit [7] association bit (A bit) specifies whether
or not address comparison is performed when writing to the UTLB address array.
In the data field, VPN is indicated by bits [31:10], D by bit [9], V by bit [8], and ASID by bits
[7:0].
The following three kinds of operation can be used on the UTLB address array:
1. UTLB address array read
VPN, D, V, and ASID are read into the data field from the UTLB entry corresponding to the
entry set in the address field. In a read, associative operation is not performed regardless of
whether the association bit specified in the address field is 1 or 0.
2. UTLB address array write (non-associative)
VPN, D, V, and ASID specified in the data field are written to the UTLB entry corresponding
to the entry set in the address field. The A bit in the address field should be cleared to 0.
3. UTLB address array write (associative)
Rev.4.00 Oct. 10, 2008 Page 97 of 1122
REJ09B0370-0400