SH7751 Datasheet, PDF (1016/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
Always write to this register prior to I/O space read and I/O space write operations by PIO
transfer.
Bits 31 to 18—I/O Space Base Address (IOBR31 to 18): Sets the base register for the PCI I/O
space in PIO transfers.
Bits 17 to 1—Reserved: These bits always return 0 when read. Always write 0 to these bits when
writing.
Bit 0—Lock Transfer (LOCK): Specifies the locking of the I/O space during PIO transfer.
Bit 0: LOCK
0
1
Description
Not locked
Locked
(Initial value)
22.2.35 PCI Power Management Interrupt Register (PCIPINT)
Bit: 31
30
29
...
11
10
9
8
—
—
—
...
—
—
—
—
Initial value:
0
0
0
...
0
0
0
0
PCI-R/W: —
—
—
...
—
—
—
—
PP Bus-R/W: R
R
R
...
R
R
R
R
Bit:
7
6
5
4
3
—
—
—
—
—
Initial value:
0
0
0
0
0
PCI-R/W: —
—
—
—
—
PP Bus-R/W: R
R
R
R
R
Note: Cleared by setting WC: 1. (Writing of 0 is ignored.)
2
1
0
— PWRST_ PWRST_
D3
D0
0
0
0
—
—
—
R
R/WC R/WC
The PCI power management interrupt register (PCIPINT) controls the power management
interrupts. It provides the interrupt bits for a transition to the power state D3 (power down mode)
and recovery to the power state D0 (normal state). This 32-bit read/write register can be accessed
from the PP bus.
Rev.4.00 Oct. 10, 2008 Page 918 of 1122
REJ09B0370-0400