SH7751 Datasheet, PDF (881/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Interrupt Controller (INTC)
Bit 7—IRL Pin Mode (IRLM): Specifies whether pins IRL3–IRL0 are to be used as level-
encoded interrupt requests or as four independent interrupt requests.
Bit 7: IRLM
0
1
Description
IRL pins used as level-encoded interrupt requests
(Initial value)
IRL pins used as four independent interrupt requests (level-sense IRQ
mode)
Bits 13 to 10 and 6 to 0—Reserved: These bits are always read as 0, and should only be written
with 0.
19.3.3 Interrupt Priority Level Settting Register 00 (INTPRI00)
The interrupt priority level setting register (INTPRI00) sets the order of priority (levels 15 to 0) of
the internal peripheral module interrupts. The INTPRI00 register is a 32-bit read/write register. It
is initialized to H'00000000 at a reset. It is not initialized in standby mode.
Bit: 31
30
29
...
19
18
17
16
...
Initial value:
0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 15
14
13
...
3
2
1
0
...
Initial value:
0
0
0
...
0
0
0
0
R/W: R/W
R/W
R/W
...
R/W
R/W
R/W
R/W
Table 19.6 shows the relationship between interrupt request sources and the respective bits of the
INTPRI00 register.
Table 19.6 Interrupt Request Sources and INTPRI00 Register
Bits
Register
31 to 28 27 to 24 23 to 20 19 to 16 15 to 12 11 to 8 7 to 4 3 to 0
Interrupt priority levelReserved
setting
register
Reserved
Reserved
Reserved
TMU ch4 TMU ch3 PCI (1) PCI (0)
Note: Reserved bits: These bits always read as 0, and should only be written with 0.
Rev.4.00 Oct. 10, 2008 Page 783 of 1122
REJ09B0370-0400