SH7751 Datasheet, PDF (58/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

3.4 TLB Functions .................................................................................................................. 78
3.4.1 Unified TLB (UTLB) Configuration ................................................................... 78
3.4.2 Instruction TLB (ITLB) Configuration................................................................ 82
3.4.3 Address Translation Method................................................................................ 82
3.5 MMU Functions................................................................................................................ 85
3.5.1 MMU Hardware Management ............................................................................. 85
3.5.2 MMU Software Management .............................................................................. 85
3.5.3 MMU Instruction (LDTLB)................................................................................. 85
3.5.4 Hardware ITLB Miss Handling ........................................................................... 86
3.5.5 Avoiding Synonym Problems .............................................................................. 87
3.6 MMU Exceptions.............................................................................................................. 88
3.6.1 Instruction TLB Multiple Hit Exception.............................................................. 88
3.6.2 Instruction TLB Miss Exception.......................................................................... 88
3.6.3 Instruction TLB Protection Violation Exception ................................................. 89
3.6.4 Data TLB Multiple Hit Exception ....................................................................... 90
3.6.5 Data TLB Miss Exception ................................................................................... 91
3.6.6 Data TLB Protection Violation Exception........................................................... 92
3.6.7 Initial Page Write Exception ................................................................................ 93
3.7 Memory-Mapped TLB Configuration............................................................................... 94
3.7.1 ITLB Address Array ............................................................................................ 94
3.7.2 ITLB Data Array 1............................................................................................... 95
3.7.3 ITLB Data Array 2............................................................................................... 96
3.7.4 UTLB Address Array........................................................................................... 97
3.7.5 UTLB Data Array 1 ............................................................................................. 98
3.7.6 UTLB Data Array 2 ............................................................................................. 99
3.8 Usage Notes ...................................................................................................................... 100
Section 4 Caches.................................................................................................................. 101
4.1 Overview........................................................................................................................... 101
4.1.1 Features................................................................................................................ 101
4.1.2 Register Configuration......................................................................................... 102
4.2 Register Descriptions ........................................................................................................ 103
4.3 Operand Cache (OC)......................................................................................................... 105
4.3.1 Configuration ....................................................................................................... 105
4.3.2 Read Operation .................................................................................................... 108
4.3.3 Write Operation ................................................................................................... 109
4.3.4 Write-Back Buffer ............................................................................................... 111
4.3.5 Write-Through Buffer.......................................................................................... 111
4.3.6 RAM Mode.......................................................................................................... 111
4.3.7 OC Index Mode ................................................................................................... 113
Rev.4.00 Oct. 10, 2008 Page lviii of xcviii
REJ09B0370-0400