SH7751 Datasheet, PDF (1074/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
• When operating as host device
The clock must be stopped only after stopping the operation of external PCI devices connected
to the PCI bus. If you stop the clock prior to stopping the external devices, access from those
external devices will cause a hang-up. Stop the clock only after checking that there is no
problem in respect to the system configuration.
One method of stopping the operation of external PCI devices is to use the PCI power
management, as discussed above. Stop the clock after switching the external PCI devices to
power state D3 (power-down mode). In this case, all external PCI devices must support PCI
power management.
• When operating in non-host mode
When operating in non-host mode, the PCI bus clock must be in external input operating mode
(PCICLK). In this case, the host device is responsible for stopping and restarting the PCI bus
clock, so it is not necessary to stop the clock using PCICLKR of the PCIC. Make sure that the
CPU receives the interrupt in accordance with the power management sequence.
22.9.3 Compatibility with Standby and Sleep
To stop all the PCIC's internal clocks, the SLEEP command must be used to transit to standby
mode. When operating in external input pin (PCICLK) operating mode, set the PCICLKSTOP bit
to 1 to stop the PCI bus clock, transit to standby, then, after recovering from standby, clear the
PCICLKSTOP bit to 0 to prevent hazards occuring in the PCI bus clock.
When using the standby command in systems using the PCI bus, first check that the system does
not hang up if the clock is stopped.
Note that the PCIC clock does not stop after transiting to sleep mode.
22.10 Port Functions
When the PCIC is operating in non-host mode, the arbitration pin of the PCI bus can be used as a
port. When using the host functions (arbitration), the port functions cannot be used. The following
six pins can be used: PCIREQ2, PCIREQ3, PCIREQ4, PCIGNT2, PCIGNT3, and PCIGNT4. The
three pins PCIREQ2, PCIREQ3, and PCIREQ4 can be used as I/O ports. The three pins
PCIGNT2, PCIGNT3, and PCIGNT4 can be used as output ports. Data is output in synchronous
with the bus clock (CKIO). Input data is fetched at the rising edge of the bus clock.
Port control is performed by the port control register (PCIPCTR) and port data register
(PCIPDTR). PCIPCTR controls the existence of the port function, the switching ON/OFF of the
pull-up resistance, and the switching between input and output. PCIPDTR performs the
input/output of port data.
Rev.4.00 Oct. 10, 2008 Page 976 of 1122
REJ09B0370-0400