SH7751 Datasheet, PDF (338/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Power-Down Modes
Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes
Status
Power-
Down Entering
Mode Conditions CPG
CPU
On-chip
On-Chip Peripheral
Memory Modules Pins
Sleep
SLEEP Operating Halted Held
instruction
(registers
executed
held)
while STBY
bit is 0 in
STBCR
Operating Held
Deep
sleep
SLEEP Operating Halted Held
instruction
(registers
executed
held)
while STBY
bit is 0 in
STBCR,
and DSLP
bit is 1 in
STBCR2
Operating Held
(DMA
halted)
Standby SLEEP Halted
instruction
executed
while STBY
bit is 1 in
STBCR
Halted Held
(registers
held)
Halted* Held
Hard- Setting CA Halted
ware pin to low
standby level
Halted
Unde- Halted*
fined
High-
imped-
ance
state
Module Setting
Operating Operating Held
standby MSTP bit to
1 in STBCR
Specified
modules
halted*
Held
External Exiting
Memory Method
Refresh- • Interrupt
ing
• Reset
Self-
• Interrupt
refresh- _{• Reset}
ing
Self-
• Interrupt
refresh- _{• Reset}
ing
Unde-
fined
• Power-on
reset
Refresh- • Clearing
ing
MSTP bit
to 0
• Reset
Note: * The RTC operates when the START bit in RCR2 is 1 (see section 11, Realtime Clock
(RTC)).
Rev.4.00 Oct. 10, 2008 Page 240 of 1122
REJ09B0370-0400