SH7751 Datasheet, PDF (230/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Caches
[4:2]:
[1:0]
LW specification Specifies longword position in SQ0/SQ1
00
Fixed at 0
4.7.3 Transfer to External Memory
Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF).
Issuing a PREF instruction for P4 area H'E000 0000 to H'E3FF FFFC starts a burst transfer from
the SQs to external memory. The burst transfer length is fixed at 32 bytes, and the start address is
always at a 32-byte boundary. While the contents of one SQ are being transferred to external
memory, the other SQ can be written to without a penalty cycle, but writing to the SQ involved in
the transfer to external memory is deferred until the transfer is completed.
The SQ transfer destination external address bit [28:0] specification is as shown below, according
to whether the MMU is on or off.
• When MMU is on
The SQ area (H'E000 0000 to H'E3FF FFFF) is set in VPN of the UTLB, and the transfer
destination external address in PPN. The ASID, V, SZ, SH, PR, and D bits have the same
meaning as for normal address translation, but the C and WT bits have no meaning with regard
to this page. Since burst transfer is prohibited for PCMCIA areas, the SA and TC bits also have
no meaning.
When a prefetch instruction is issued for the SQ area, address translation is performed and
external address bits [28:10] are generated in accordance with the SZ bit specification. For
external address bits [9:5], the address prior to address translation is generated in the same way
as when the MMU is off. External address bits [4:0] are fixed at 0. Transfer from the SQs to
external is performed to this address.
• When MMU is off
The SQ area (H'E000 0000 to H'E3FF FFFF) is specified as the address at which a PREF
instruction is issued. The meaning of address bits [31:0] is as follows:
[31:26]:
[25:6]:
[5]:
111000
Address
0/1
[4:2]:
[1:0]
Don't care
00
Store queue specification
External address bits [25:6]
0: SQ0 specification
1: SQ1 specification and external address bit [5]
No meaning in a prefetch
Fixed at 0
External address bits [28:26], which cannot be generated from the above address, are generated
from the QACR0/1 registers.
Rev.4.00 Oct. 10, 2008 Page 132 of 1122
REJ09B0370-0400