SH7751 Datasheet, PDF (553/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
CKIO
Bank
Precharge-sel
Address
Tr
Trw
Tc1
Tc2
Tc3 Tc4/Td1 Td2
Td3
Td4
Td5
Td6
Td7
Td8
Tpc
Row
Row
H/L
Row
c1
CSn
RD/WR
RAS
CASS
DQMn
D31–D0
(read)
c1
c2
c3
c4
c5
c6
c7
c8
BS
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.39 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8)
In a cycle of access to synchronous DRAM, the BS signal is asserted for one clock cycle at the
beginning of a bus cycle. Data are accessed in the following sequence: in the fill operation for
a cache miss, the data between the 32-bit boundaries that include the missed data are first read;
after that, the data between 32-byte boundaries that include the missed data are read in a
wraparound way.
Rev.4.00 Oct. 10, 2008 Page 455 of 1122
REJ09B0370-0400