SH7751 Datasheet, PDF (605/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
Bit:
Initial value:
R/W:
31
SSA2
0
R/W
30
SSA1
0
R/W
29
SSA0
0
R/W
28
STC
0
R/W
27
DSA2
0
R/W
26
DSA1
0
R/W
25
DSA0
0
R/W
24
DTC
0
R/W
Bit: 23
22
21
20
19
18
17
16
—
—
—
—
DS
RL
AM
AL
Initial value:
0
0
0
0
—
—
—
—
R/W: R
R
R
R
R/W (R/W) R/W (R/W)
Bit: 15
14
13
12
11
10
9
8
DM1 DM0
SM1
SM0
RS3
RS2
RS1
RS0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
TM
TS2
TS1
TS0
—
IE
TE
DE
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R
R/W R/(W) R/W
Notes: The TE bit can only be written with 0 after being read as 1, to clear the flag.
The RL, AM, AL, and DS bits may be absent, depending on the channel.
DMA channel control registers 0–3 (CHCR0–CHCR3) are 32-bit readable/writable registers that
specify the operating mode, transfer method, etc., for each channel. Bits 31–28 and 27–24 indicate
the source address and destination address, respectively; these settings are only valid when the
transfer involves the CS5 or CS6 space and the relevant space has been specified as a PCMCIA
interface space. In other cases, these bits should be cleared to 0. For details of the PCMCIA
interface, see section 13.3.7, PCMCIA Interface.
Bits 18 and 16 are not present in CHCR2 and CHCR3. In CHCR2 and CHCR3, these bits cannot
be modified (for write, a write value of 0 should always be used) and are always read as 0.
These registers are initialized to H'00000000 by a power-on or manual reset. They retain their
values in standby mode, sleep mode, and deep sleep mode.
Rev.4.00 Oct. 10, 2008 Page 507 of 1122
REJ09B0370-0400