SH7751 Datasheet, PDF (290/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Instruction Set
Addressing Instruction
Mode
Format
Effective Address Calculation Method
Register
@(disp:4, Rn) Effective address is register Rn contents with
indirect with
4-bit displacement disp added. After disp is
displacement
zero-extended, it is multiplied by 1 (byte), 2 (word),
or 4 (longword), according to the operand size.
Rn
disp
(zero-extended)
+
×
Rn + disp × 1/2/4
Calculation
Formula
Byte: Rn +
disp → EA
Word: Rn +
disp × 2 → EA
Longword:
Rn + disp × 4
→ EA
Indexed
register
indirect
@(R0, Rn)
1/2/4
Effective address is sum of register Rn and R0
contents.
Rn
+
Rn + R0
Rn + R0 → EA
GBR indirect @(disp:8,
with
GBR)
displacement
R0
Effective address is register GBR contents with
8-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2 (word),
or 4 (longword), according to the operand size.
GBR
disp
+
(zero-extended)
×
GBR
+ disp × 1/2/4
Byte: GBR +
disp → EA
Word: GBR +
disp × 2 → EA
Longword:
GBR + disp ×
4 → EA
1/2/4
Indexed
@(R0, GBR) Effective address is sum of register GBR and R0
GBR indirect
contents.
GBR
+
GBR + R0
GBR + R0 →
EA
R0
Rev.4.00 Oct. 10, 2008 Page 192 of 1122
REJ09B0370-0400