SH7751 Datasheet, PDF (39/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
22.2.3 PCI
864
Configuration Register 2
(PCICONF2)
22.2.17 PCI Control 886
Register (PCICR)
887
22.2.24 PCI Arbiter 900
Interrupt Register
(PCIAINT)
901
Revision (See Manual for Details)
Description amended
Bits 23 to 16—Sub Class Codes (CLASS15 to 8): Shows the
subclass code. For details, please see appendix D, Pin
Functions of the PCI Local Bus Specifications, Revision 2.1.
Bits 15 to 8—Register Level Programming Interface (CLASS7
to 0): Shows the register level programming interface. For
details, please see appendix D, Pin Functions of the PCI Local
Bus Specifications, Revision 2.1.
Description added of Bit 3
Bit 3: SERR
0
1
Description
SERR pin at Hi-Z (driven to High by pull-up resistor)
Assert SERR (Low output)
(Initial value)
Description deleted of Bit 1
Description amended
The PCIAINT register is initialized to H'00000000 at a power-on
reset or software reset.
Description added of Bit 13
Bit 13—Master Broken Interrupt (MST_BRKN): Detects when
the master granted with bus privileges does not start a
transaction (FRAME not asserted) within 16 clocks. For the
SH7751, see 22.12, Usage Notes.
Description added of Bit 12
Bit 12—Target Bus Timeout Interrupt (TGT_BUSTO): Neither
TRDY nor STOP are not returned within 16 clocks in the case
of the first data transfer, or within 8 clocks in the case of second
and subsequent data transfers. For the SH7751, see 22.12,
Usage Notes.
Description added of Bit 11
Bit 11—Master Bus Timeout Interrupt (MST_BUSTO): Indicates
the detection that IRDY was not asserted within 8 clock cycles
in a transaction initiated by a device including PCIC.
Description amended of Bit 1
Bit 1—Write Data Parity Error Interrupt (DPERR_WT): Indicates
the detection of the assertion of PERR in a data write operation
when a device other than the PCIC is operating as the bus
master.
Rev.4.00 Oct. 10, 2008 Page xxxix of xcviii
REJ09B0370-0400