SH7751 Datasheet, PDF (224/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Caches
In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address
array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which
association is not performed. Data field bits [31:29] are used for the virtual address specification
only in the case of a write in which association is performed.
The following three kinds of operation can be used on the IC address array:
1. IC address array read
The tag and V bit are read into the data field from the IC entry corresponding to the way and
entry set in the address field. In a read, associative operation is not performed regardless of
whether the association bit specified in the address field is 1 or 0.
2. IC address array write (non-associative)
The tag and V bit specified in the data field are written to the IC entry corresponding to the
way and entry set in the address field. The A bit in the address field should be cleared to 0.
3. IC address array write (associative)
When a write is performed with the A bit in the address field set to 1, each way's tag stored in
the entry specified in the address field is compared with the tag specified in the data field. The
way number set in bit [13] is ignored. If the MMU is enabled at this time, comparison is
performed after the virtual address specified by data field bits [31:10] has been translated to a
physical address using the ITLB. If the addresses match and the V bit in that way is 1, the V bit
specified in the data field is written into the IC entry. In other cases, no operation is performed.
This operation is used to invalidate a specific IC entry. If an ITLB miss occurs during address
translation, or the comparison shows a mismatch, an interrupt is not generated, no operation is
performed, and the write is not executed. If an instruction TLB multiple hit exception occurs
during address translation, processing switches to the instruction TLB multiple hit exception
handling routine.
31
24 23
Address field _{1 1 1 1 0 0 0 0}
31
Data field
Tag
13 12
Entry
Way
10 9
543210
A
10
V
Legend:
V: Validity bit
A: Association bit
: Reserved bits (0 write value, undefined read value)
Figure 4.12 Memory-Mapped IC Address Array
Rev.4.00 Oct. 10, 2008 Page 126 of 1122
REJ09B0370-0400