SH7751 Datasheet, PDF(1214/1224 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SH7751 Datasheet, PDF (1214/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

◁

G. Power-On and Power-Off Procedures

â¯ When the LSI is mounted on a board and connected to other elements, ensure that â0.3 V <

Vin < VDDQ + 0.3 V. In addition, the time limit for the fall of power supply VDDQ and power

supply VDD from the minimum values in the LSIâs guaranteed operation voltage range (VDDQ

(min.) and VDD (min.)) to VDDQ â¥ 1.0 V or VDD â¥ 0.5 V, respectively, is 150 ms (max.), as

shown in figure G.3. The product may be damaged if this time limit is exceeded. It is

recommended that the power-off sequence be completed in as short a time as possible.

Notes: 1. Note on Power-On

If the below conditions (A) are not met during power-on, PLL2 may not oscillate

correctly and CKIO may not be output properly.

Conditions (A):

VDDQ (VDDQ, V , DD-CPG V ) DD-RTC is 2.0 V or above when VDD ( VDD, V , DD-PLL1 V ) DD-PLL2 is 1.2 V

or above.

2. Workarounds

Any of methods (1) to (3) below may be used to avoid the problem by stopping PLL2

oscillation temporarily.

(1) As shown in figure G.1, select mode 6*1 immediately after power-on, select the

desired clock mode once the above conditions (A) are satisfied, and cancel the

power-on reset.

(2) After starting with clock operation mode 6*1 selected, change FRQCR to specify

the desired frequency clock.

Note: It is not possible to use frequency divider 1 when this method is employed.

(3) Temporarily stop PLL2 by writing 0 to FRQCR.PLL2EN. After maintaining

FRQCR.PLL2EN as 0 for 1 Âµs or more, write 1 to FRQCR.PLL2EN to restart

PLL2.

Note: If this method is used, the clock output from CKIO cannot be guaranteed

until the above operations are completed. If abnormal signal output is produced, the

frequency is higher than normal. Therefore, it is possible that unwanted noise may

be generated from the clock line or, if the LSIâs CKIO pin is used to supply a clock

to another device, the clock may not be supplied correctly to the external device.

When using this method, it is recommended that sufficient verification testing be

performed on the actual system.

Rev.4.00 Oct. 10, 2008 Page 1116 of 1122

REJ09B0370-0400

▷