SH7751 Datasheet, PDF (747/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Serial Communication Interface (SCI)
1
Serial
data
Start
bit
Data
Multi-
proces- Stop
sor bit bit
0 D0 D1
D7 1 1
Start
bit
Data
Multi-
proces- Stop Start
sor bit bit bit
Multi-
Data proces- Stop
sor bit bit
1
0 D0 D1
D7 0 1 0 D0 D1
D7 0 ^{Idle state}
(mark state)
TDRE
TEND
One frame
Data written to SCTDR1
and TDRE flag cleared
to 0 by TXI interrupt
handler
MPBT bit cleared to 0, data
written to SCTDR1, and
TDRE flag cleared to 0 by
TEI interrupt handler
TXI interrupt
request
TEI interrupt
request
Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit)
Multiprocessor Serial Data Reception
1. Method for determining whether an interrupt generated during receive operation is a
multiprocessor interrupt
When an interrupt such as RXI occurs during receive operation using the on-chip SCI
multiprocessor communication function, check the state of the MPIE bit in the SCSCR1
register as part of the interrupt handling routine.
a. If the MPIE bit in the SCSCR1 register is set to 1
Ignore the received data.
Data with the multiprocessor bit (MPB) set to 0 and intended for another station was
received, and the RDRF bit in the SCSCR1 register was set to 1. Therefore, clear the
RDRF bit in the SCSCR1 register to 0.
b. If the MPIE bit in the SCSCR1 register is cleared to 0
A multiprocessor interrupt indicating that data (ID) with the multiprocessor bit (MPB) set
to 1 was received, or a receive data full interrupt (RXI) occurred when data with the
multiprocessor bit (MPB) set to 0 and intended for this station was received.
2. Method for determining whether received data is ID or data
Do not use the MPB bit in the SCSSR1 register for software processing.
Rev.4.00 Oct. 10, 2008 Page 649 of 1122
REJ09B0370-0400