SH7751 Datasheet, PDF (810/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Serial Communication Interface with FIFO (SCIF)
Figure 16.12 shows an example of the operation for reception.
Start
1 _bit
Data
Parity Stop Start
bit bit bit
Data
Parity Stop
bit bit
Serial
0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 0
0/1
data
RDF
FER
RXI interrupt
request
One frame
Data read and RDF flag
read as 1 then cleared to
0 by RXI interrupt handler
ERI interrupt request
generated by receive
error
Figure 16.12 Example of SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit)
5. When modem control is enabled, the RTS2 signal is output when SCFRDR2 is empty. When
RTS2 is 0, reception is possible. When RTS2 is 1, this indicates that SCFRDR2 contains a
number of data bytes equal to or greater than the RTS2 output active trigger set number. The
RTS2 output active trigger value is specified by bits 10 to 8 in the FIFO control register
(SCFCR2), described in section 16.2.9, FIFO Control Register (SCFCR2). RTS2 also goes to 1
when bit 4 (RE) in SCSCR2 is 0.
Figure 16.13 shows an example of the operation when modem control is used.
Serial data
RxD2
Start
bit
0 D0 D1 D2
Parity Stop
bit bit
D7 0/1 1
Start
bit
0
RTS2
Figure 16.13 Example of Operation Using Modem Control (RTS2)
Rev.4.00 Oct. 10, 2008 Page 712 of 1122
REJ09B0370-0400