SH7751 Datasheet, PDF (280/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Floating-Point Unit
The FPSCR FPU exception cause field contains bits corresponding to all of above E, V, Z, O,
U, and I, and the FPSCR flag and enable fields contain bits corresponding to V, Z, O, U, and I,
but not E. Thus, FPU errors cannot be disabled.
When an FPU exception occurs, the corresponding bit in the FPU exception cause field is set
to 1, and 1 is added to the corresponding bit in the FPU exception flag field. When an FPU
exception does not occur, the corresponding bit in the FPU exception cause field is cleared to
0, but the corresponding bit in the FPU exception flag field remains unchanged.
• Enable/disable exception handling
The FPU supports enable exception handling and disable exception handling.
Enable exception handling is initiated in the following cases:
⎯ FPU error (E): FPSCR.DN = 0 and a denormalized number is input
⎯ Invalid operation (V): FPSCR.EN.V = 1 and (instruction = FTRV or invalid operation)
⎯ Division by zero (Z): FPSCR.EN.Z = 1 and division with a zero divisor
⎯ Overflow (O): FPSCR.EN.O = 1 and instruction with possibility of operation result
overflow
⎯ Underflow (U): FPSCR.EN.U = 1 and instruction with possibility of operation result
underflow
⎯ Inexact exception (I): FPSCR.EN.I = 1 and instruction with possibility of inexact operation
result
For information on possibilities (which differ depending on the individual instruction), see
section 9, Instruction Descriptions, in the SH-4 Software Manual. All exception events that
originate in the FPU are assigned as the same exception event. The meaning of an exception is
determined by software by reading system register FPSCR and interpreting the information it
contains. If no bits are set in the FPU exception cause field of FPSCR when one or more of bits
O, U, I, and V (in case of FTRV only) are set in the FPU exception enable field, this indicates
that an actual FPU exception is not generated. Also, the destination register is not changed by
any FPU exception handling operation.
Except for the above, the bit corresponding to V, Z, O, U, or I is set to 1 in all processing, and
the default value is generated as the result of the operation.
⎯ Invalid operation (V): qNAN is generated as the result.
⎯ Division by zero (Z): Infinity with the same sign as the unrounded value is generated.
⎯ Overflow (O):
In round to zero mode, the maximum normalized number, with the same sign as the
unrounded value, is generated.
In round to nearest mode, infinity with the same sign as the unrounded value is generated.
Rev.4.00 Oct. 10, 2008 Page 182 of 1122
REJ09B0370-0400