SH7751 Datasheet, PDF (437/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Name
Signals
I/O
Column address CAS0/DQM0 O
strobe 0
Column address CAS1/DQM1 O
strobe 1
Column address CAS2/DQM2 O
strobe 2
Column address CAS3/DQM3 O
strobe 3
Ready
Area 0 MPX
interface
specification/
16-bit I/O
RDY
I
MD6/IOIS16 I
Clock enable
Bus release
request
Bus use
permission
Area 0 bus
width/PCMCIA
card select
CKE
O
BREQ/
I
BSACK
BACK/
O
BSREQ
MD3/CE2A*¹ I/O
MD4/CE2B*²
Endian switchover MD5
I
Master/slave
switchover
MD7/CTS2
I/O
DMAC0
DACK0
O
acknowledge
signal
DMAC1
DACK1
O
acknowledge
signal
13. Bus State Controller (BSC)
Description
When setting DRAM interface: CAS signal for
D7–D0
When setting synchronous DRAM interface:
selection signal for D7–D0
When setting DRAM interface: CAS signal for
D15–D8
When setting synchronous DRAM interface:
selection signal for D15–D8
When setting DRAM interface: CAS signal for
D23–D16
When setting synchronous DRAM interface:
selection signal for D23–D16
When setting DRAM interface: CAS signal for
D31–D24
When setting synchronous DRAM interface:
selection signal for D31–D24
Wait state request signal
In power-on reset: Designates area 0 bus as MPX
interface (1: SRAM, 0: MPX)
When setting PCMCIA interface: 16-bit I/O
designation signal. Valid only in little-endian mode.
Synchronous DRAM clock enable control signal
Bus release request signal/bus acknowledge signal
Bus use permission signal/bus request
In power-on reset: area 0 bus width specification
signal
When using PCMCIA: CE2A, CE2B
Endian specification in a power-on reset
Indicates master/slave status in a power-on reset
Serial interface CTS2
DMAC channel 0 data acknowledge
DMAC channel 1 data acknowledge
Rev.4.00 Oct. 10, 2008 Page 339 of 1122
REJ09B0370-0400