SH7751 Datasheet, PDF (1077/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
PCICLK
AD[31:0]
C/BE[3:0]
FRAME
IRDY
DEVSEL
TRDY
STOP
A
C
(High)
0 12345 678
DD
BE BE
DDDD DD
BE BE BE BE BE BE
PCIAINT: Bit 12 asserted
Figure 22.25 Target Bus Timeout Interrupt Generation Example 2
(Example in which the Target Device Takes 8 Clock Cycles to Prepare for the Third Data
Transfer)
PCICLK
AD[31:0]
C/BE[3:0]
FRAME
IRDY
DEVSEL
TRDY
STOP
0 1 2 3 4 56 78
A
DDDDD DD
C
BE BE BE BE BE BE BE
(High)
PCIAINT: Bit 11 asserted
Figure 22.26 Master Bus Timeout Interrupt Generation Example 1
(Example in which the Master Device Prepares the Data and Asserts IRDY at the Eighth
Clock Cycle after FRAME Was Asserted)
Rev.4.00 Oct. 10, 2008 Page 979 of 1122
REJ09B0370-0400